For LTPS with regularly-arranged atoms, it has high carrier mobility (10 to 300 cm2/Vs) and can provide a large driving current, so it may be used to accelerate the response time for liquid crystals, reduce a volume of a TFT and increase a transmittance area, thereby to achieve higher brightness and resolution. As a result, the LTPS has been widely used to manufacture an active layer in a process of manufacturing the TFT.
Referring to FIG. 1 and FIG. 2, which are schematic views of an LTPS TFT array substrate in the related art, 10 represents a base substrate, 11 represents a buffer layer, 13 represents an active layer, 14 represents a gate insulating layer, 15 represents a gate electrode, 16 represents an interlayer insulating layer, 170 represents a source electrode, and 171 represents a drain electrode. When manufacturing the array substrate in FIG. 1, a thickness of the gate insulating layer 14 plus the interlayer insulating layer 16 is larger than that of the active layer 13 (generally the thickness of the gate insulating layer plus the interlayer insulating layer is more than 10 times that of the active layer), and films are deposited and etched unevenly. Hence, in order to ensure contact holes to reach the active layer on the entire substrate, it is required for the contact holes by overetching the gate insulating layer and the interlayer insulating layer to a great extent. In the case that the gate insulating layer and the interlayer insulating layer are overetched, the relatively thin active layer will easily be overetched too. At this time, an ohmic contact between the source/drain electrodes and the active layer will be adversely affected and an on-state current will be decreased. As a result, the TFT characteristics and thereby the display of the display device will be adversely affected.